1. Field of the Invention
The present invention relates to an On-Chip network (OCN) based moving picture decoder; and, more particularly, to an On-Chip network based H.264 decoder having a star-mesh mixed structure for providing a moving picture decoder based on an On-Chip Network that globally has a mesh structure and locally has a star structure in order to embody a System on Chip (SoC) corresponding to a moving picture decoder having improved data communication parallelism.
This work was supported by the IT R&D program of MIC/IITA [2005-S-077-03, “Development of On-Chip Network Based SoC Platform”].
2. Description of Related Art
According to the development of a semiconductor process technology, a System on Chip (SoC) design was introduced. The system on Chip (Soc) design is a technology that mounts a processor, a memory, and various peripheral devices on a chip. The goal of the SoC design is to integrating various verified intellectual properties on a chip so as to enable a corresponding chip to perform various functions.
In the semiconductor field, the intellectual property (IP) is defined as a semiconductor design module that is a reusable and independent function block in a semiconductor integrated circuit design. For example, the IP denotes a hardware or software functional block to form a semiconductor logic circuit.
In the SoC design, an On-Chip Network structure was introduced for enabling IPs to mutually communicate with each others. That is, the On-Chip Network structure has the same feature of a computing network.
As the OCN structure, an AMBA high performance bus of AMBA 2.0, which is a single On-Chip Bus, an advanced system bus, and an advanced peripheral bus were generally used, where AMBA stands for an advanced micro-controller bus architecture.
As described above, the AMBA supports data communication among IPs through a single shared bus. That is, the AMBA allows only one slave module to transmit/receive data to/from a master module through the single shared bus at a time. Such a way of transmitting/receiving data of the AMBA is inefficient in views of system throughput and resource utilization.
Lately, a moving picture decoder was designed based on the On-Chip network. In generally, a moving picture decoder was embodied by integrating a plurality of master modules and a plurality of slave modules on an On-chip bus based on the AMBA.
In order to satisfy various demands of a user for a moving picture decoder, it is required to integrate a plurality of master modules and slave modules on an On-Chip Network for performing different functions. As the number of master modules increases, the IP integration becomes more complicated. Particularly, the performance of a moving picture decoder abruptly deteriorates due to the bottleneck that is caused by frequency data communication among a plurality of mater modules.
In order to overcome the problem, the AMBA introduced multi-layer AHB/APB On-Chip Network. As another method, a crossbar switch was embodied on an On-Chip Network.
However, DMAC is not allowed to transmit data while a CPU generates a control signal for a predetermined slave module in the multi-layer AHB/APB On-Chip Network. That is, data transmission is delayed as long as a time that the CPU occupies a bus. The data parallelism is limited thereby.
In the crossbar switch based On-Chip Network, the data parallelism is limited by the number of master modules and the functional characteristics of a slave module. That is, a channel is not provided on a switch to transmit data between slave modules although a channel is provided to transmit data between a mater module and a slave module.
That is, the performance of an On-Chip Network based moving picture decoder depends on how to design the structure of an On-Chip Network to improve the data parallelism and how to cluster intellectual properties related to a moving picture decoding function.
Therefore, there is a demand for a technology for improving the data parallelism by dividing slave modules for transmitting and receiving data among intellectual properties, clustering the divided slave modules on an On-Chip Network, and effectively designing the structure of an On-Chip Network.